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In this paper a novel user-friendly implementation of an all-digital phase-locked loop (ADPLL) is presented.Its novelty lies in the fact that the very basic functions of the ADPLL are kept in the top module Verilog file.Against the normal design practice, all of the main math functions were implemented using the sub-modules placed outside but called from within the top module.This way ADPLL can be...
As device feature size continues to shrink, reliability becomes a severe issue due to process variation, particle-induced transient errors, and transistor wear-out/stress such as Negative Bias Temperature Instability (NBTI). Unless this problem is addressed, chip multi-processor (CMP) systems face low yields and short mean-time-to-failure (MTTF). This paper proposes a new design framework for multi-core...
In this paper, we present an example-based system for terrain synthesis. In our approach, patches from a sample terrain (represented by a height field) are used to generate a new terrain. The synthesis is guided by a user-sketched feature map that specifies where terrain features occur in the resulting synthetic terrain. Our system emphasizes large-scale curvilinear features (ridges and valleys) because...
The certainty equivalence principle is used to combine a robust adaptive law with a control structure derived from the linear quadratic (LQ) control problem. The resulting adaptive control scheme is applicable to minimum and non-minimum phase continuous-time plants and is robust with respect to unmodeled dynamics and bounded disturbances. The computational complexity of the continuous-time adaptive...
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