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This paper reports a novel generation of CMOS stress mapping chips comprising 32 square field effect transistors (FET) with four source/drain contacts (piezo-FETs) exploiting the shear piezoresistive effect in n-type (NMOS) or p-type (PMOS) inversion layers. The sensor chips with a total die area of 2.5 times 2 mm2 are integrated with analog circuitry and digital logic. When exposed to homogenous...
This paper reports on a CMOS-based stress sensor array used to characterize the distribution of mechanical in-plane stress in the surface of packaged integrated circuit dies. It consists of an array of 32 stress sensors exploiting the shear piezoresistive effect in silicon. The stress sensor elements are integrated in a mixed-signal system consisting of analog switches, an amplifier stage, a successive-approximation...
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