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The total performance of low-k/Cu interconnects featuring short turnaround-time (TAT) silylated scalable porous silica (Po-SiO, k = 2.1) with high porosity (50%) is demonstrated. The TAT for the film formation process including silylation treatment is about 25% reduced by adding a promoter, causing reinforcement of the film. Applying this improved Po-SiO, a 140-nm-pitch dual-damascene structure is...
A feasibility study of 70 nm pitch 2-level dual damascene interconnects featuring EUV lithography is presented. Using Ru barrier metal and scalable porous silica (Po-SiO, k=2.1), a low resistivity below 4.5 ????cm and a 13% reduction in wiring capacitance compared with porous SiOC (k=2.65) was obtained. The predicted circuit-performance using Po-SiO was 10% higher than that with porous SiOC. The electromigration...
The resistance of wiring with a width of less than 40 nm was firstly evaluated by using an EUV lithography (lambda=13.5 nm). The resistance was quite high in narrow wiring with conventional Ta barrier film, while a very low effective resistivity rhoeff of lower than 4.5 muOmega cm was obtained by using PVD-Ru barrier film. This difference was attributed to combination of thinner barrier metal films...
A comprehensive study of low-k/Cu integration featuring short TAT (turnaround time) silylated scalable porous silica (Po-SiO, k=2.1) with high porosity (50%) is presented. The TAT for silylation is about 25% reduced by adding a promoter, causing reinforcement of the film. Applying this improved Po-SiO, 140 nm pitch dual damascene structure is successfully achieved. The wiring capacitance showed 10%...
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