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We take the paradigm of cloud computing developed in the cyber-world and put it into the physical world to create a cyber-physical computing cloud. A server in this cloud moves in space making it a vehicle with physical constraints. Such vehicles also have sensors and actuators elevating mobile sensor networks from a deployment to a service. Possible hosts include cars, planes, people with smartphones,...
In this paper, we present a new erase gate disturb mechanism during programming of selected cell for split-gate Flash memory. This type of disturb occurs on the programmed cell sharing the same erase gate as the selected cell. The disturb is due to electron-loss from floating gate to erase gate caused by low-field Fowler-Norheim (F-N) tunneling. We proposed a method that adds extra bias voltages at...
The electron and hole injection statistics of BE-SONOS NAND Flash is studied for the first time using a 75 nm charge-trapping NAND Flash test chip. By using the incremental step pulse programming (ISPP) method the impact of device variations are minimized and the electron number (N) fluctuation can be identified. We find that both electron and hole injection statistics well follow the Poisson statistics...
Floating gate (FG) devices using barrier-engineered (BE) tunneling dielectric have been studied both theoretically and experimentally. Through WKB modeling the tunneling efficiency of various multi-layer tunneling barriers can be well predicted. Experimental results for FG devices with oxide-nitride-oxide (ONO) U-shaped barrier are examined to validate our model. Furthermore, a large-density array...
Gate stack etch profile-induced reliability issues are reviewed and discussed. A taper nitride profile, which blocks source/drain (S/D) implantation, induces an unwanted n- region. In other words, residual charges above the junctions can deplete the n- much easily and cut off the channel formation. This will cause poor string resistance distribution, worse endurance behavior, program and erase (P/E)...
We demonstrate for the first time a fluorine incorporated band- engineered (BE) tunnel oxide (SiO2/HfSiO/SiO2) TANOS with excellent program / erase (P/E) characteristics and endurance to 105 cycles. Incorporating fluorine in the tunnel dielectric improves Si/SiO2 interface resulting in excellent endurance of nearly constant over 3 V P/E window for at least 105 cycles. Fluorine also reduces interface...
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