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FinFET has become the mainstream logic device architecture in recent technology nodes due to its superior electrostatic and leakage control [1,2,3,4]. However, parasitic capacitance has been a key performance detractor in 3D FinFETs. In this work, a novel low temperature ALD-based SiBCN material has been identified, with an optimized spacer RIE process developed to preserve the low-k value and provide...
Multi-layer SiN barrier film with high breakdown and low leakage is developed for Cu low k interconnects and is compared with the SiCNH barrier film used at previous technology nodes. Ultra-thin SiN barrier cap film also provides high conformality and fills recess in Cu lines observed post CMP. A significant enhancement in electro migration (EM) performance was obtained by selectively depositing Co...
Critical parameters of low-k films were defined to keep capacitance benefit and TDDB reliability in the scaling BEOL module, according to various analyses. In order to meet the criteria of high carbon content, low porosity with small pores, and high adhesion strength with less adhesion layer, precursor and process were designed for the SiOCH with k∼2.5. The benefits in integration and reliability...
Integration challenges of porous ultra low-k (ULK) materials resulting from the ULKs' high sensitivity to process damage constitute a major roadblock to their implementation in back-end-of-the-line wiring structures for advanced technology nodes. The Post Porosity Plasma Protection strategy, which we introduced last year, enables to shield the ULKs' porosity during key integration steps. We report...
While the spacing of interconnect structures has continued to scale with technology generation, operating voltages have not scaled accordingly leading to inevitable higher electric fields across BEOL dielectrics. Moreover, the introduction of ULK materials with lower dielectric constant is necessary to scale capacitance, however, this comes at a significant increase in integration complexity and reliability...
Fundamental material interactions as pertinent to nano-scale copper interconnects were studied for CVD Co with a variety of micro-analytical techniques. Native Co oxide grew rapidly within a few hours (XPS). Incorporation of oxygen and carbon in the CVD Co films (by AES and SIMS) depended on underlying materials, such as Ta, TaN, or Ru. Copper film texture (by XRD) and agglomeration resistance (by...
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