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A time-to-digital converter (TDC) is a key element for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. To build high-resolution TDCs, many researchers have focused on minimizing the unit delay of quantization. Vernier delay-line-based TDCs [1] are a good example. Their performance, however, is limited...
A single loop low tracking jitter pixel clock generator is demonstrated in 28nm CMOS process. The proposed architecture only consists of a conventional single loop wide bandwidth fractional-N PLL and two synchronization skills which suppress the tracking jitter and bring out the delay control function like a DLL. When a 250MHz pixel clock is generated and synchronized with a 10kHz HSYNC, the measured...
The first synchronous cyclic TDC is proposed in 28nm CMOS process. A novel 2x time amplifier whose gain is insensitive to variations and noise is proposed by using time conservative nature of the proposed synchronous time adder. The implemented 12b TDC occupies 0.01 mm2, consumes 820µW and it achieves 0.63ps of resolution over 2.6ns of input range.
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