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We present the design and simulation of information processing hardware that is comprised of single domain, Co/Pt magnets (i.e., out-of-plane nanomagnet logic — or oNML). We first describe the design and evaluation of oNML hardware that can identify instances of a preprogrammed bit sequence in streaming data. Systolic arrays (that process information using Boolean logic gates) are employed as a system-level...
A new scalable compact model for the resistive substrate network of multi-finger MOSFETs is presented. The model is based on the transmission line formalism to capture the distributed nature of the well resistance. Due to its physical foundation, the model provides a more accurate description of different layout styles over a wide range of geometries. The model is validated experimentally on a 90...
A parasitic PNP initiated Vcc latchup failure mechanism was identified as the cause of a blown via contact failure mode. Highly resistive via contacts connecting the underlying N-well substrate to its upper layer Vcc metal bus lines were consistently observed at failing circuits. A defective tungsten (W) plug was determined to be the root cause of the failure mechanism. Based on an established failure...
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