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We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic VT-variability performances are obtained (AVT=1.45mV.μm). This leads to 6T-SRAM cells with good characteristics down to VDD=0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σSNM<;SNM/6) down to VDD=0.7V. We...
Three-dimensional multi-channel field-effect transistor (MCFET) gate stack and series resistance are investigated and optimized by specifically developed integration processes, characterization methods, and numerical simulations. First, the impact of a TiN/HfO2 gate stack on embedded-gate MCFET structure performance is studied. Both TiN/SiO2 and N+poly-Si/SiO2 gate stacks were introduced in the MCFET...
For the first time, we integrated and compared the electrical performances of high-K / metal embedded gate in 3D multi-channel CMOSFETs (MCFETs) on SOI. The electrical characteristics of embedded gates obtained by filling cavities with TiN/HfO2, TiN/SiO2 or N+ poly-Si/SiO2 were compared to a planar reference. In particular we investigated electron and hole mobility behaviours (300 K down to 20 K)...
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