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Inductive effect becomes important for on-chip global interconnects, like Power/Ground (P/G) grid. Partial reluctance (the inverse of partial inductance) has been accepted to model inductive effect, for its local property. In this paper, a new method which makes full use of the structure regularity of P/G grid is proposed. With a reuse scheme and carefully handling of boundary effect, the proposed...
As the number of on die transistors continues to increase, whether it is possible to generate a near optimum P/G grid automatically in early design stage will significantly affects design closure. In this paper, optimal conditions for P/G grid automatic generation are discussed. We prove that for regular grid, there does not exist a global optimal point at which both metal usage and maximal voltage...
In multi-layered power/ground (P/G) networks, to connect the whole network together, vertical vias are usually placed at intersections between metal wires of adjoining layers. In this paper, a deep study about the design of vertical vias is presented. First we present an efficient heuristic algorithm based on sensitivity analysis to optimize via allocation in early design stage. Compared with even...
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