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This article consists of a collection of slides from the author's conference presentation. Some of the specific areas/topics discussed include: Approaches to 3D; MITLL SOI-based process; Requirements for 3D integration; Heterogeneous 3D circuit demonstrations; and Concluding remarks
We characterized TID effects in MITLL 3DIC technology. We found that the effects were comparable for nFETs on the bottom tier with that on single tier wafers. Less positive charge build-up is observed for wide nFETs on the upper tiers, and this is due to the absence of silicon below the BOX. Other results indicate that MITLL 3DIC technology can be hardened to ionizing radiation by modifying the BOX.
A 32 nm gate-first high-k/metal-gate technology is demonstrated with the strongest performance reported to date to the best of our knowledge. Drive currents of 1340/940 muA/mum (n/p) are achieved at Ioff=100 nA/mum, Vdd=1 V, 30 nm physical gate length and 130 nm gate pitch. This technology also provides a high-Vt solution for high-performance low-power applications with its high drive currents of...
This paper describe the process and test results after single tier circuit fabrication as well as after three-tier integration, determine impact of 3D vias on ring oscillator performance, and demonstrate functionality of single and multi-tier circuits of varying complexity.
In this paper, we describe details of our bonding protocol for 150-mm diameter wafers, leading to a 50% increase in oxide-oxide bond strength and demonstration of +/--0.5 mum wafer-to-wafer alignment accuracy. We have established design rules for our 3DIC technology, have quantified process factors limiting our design-rule 3D via pitch, and have demonstrated next generation 3D vias with a 2x size...
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