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While neural networks demonstrate stronger capabilities in pattern recognition nowadays, they are also becoming larger and deeper. As a result, the effort needed to train a network also increases dramatically. In many cases, it is more practical to use a neural network intellectual property (IP) that an IP vendor has already trained. As we do not know about the training process, there can be security...
Logic encryption algorithms have gained wide popularity to safeguard Integrated Circuits (ICs) from being pirated or counterfeited in untrusted third-party foundries. However, an untrusted foundry can reverse engineer the netlist and gain important insight regarding the design of a chip. In this paper, we demonstrate how an adversary can monitor side-channel information of an activated chip and analyze...
An exhaustive search based topology error detection method for power systems is presented in this paper. The method is based on minimization of the measurement residual. Power systems completely observable by PMUs is considered here. Realtime voltage and current measurements from PMUs are simulated using real time digital simulator (RTDS). The simulation considers both GTNET and hardware PMUs. The...
Artificial Neural Networks (ANNs) have found widespread applications in tasks such as pattern recognition and image classification. However, hardware implementations of ANNs using conventional binary arithmetic units are computationally expensive, energy-intensive and have large area overheads. Stochastic Computing (SC) is an emerging paradigm which replaces these conventional units with simple logic...
In contrast to other studies in IC supply chain security where foundries are classified as either untrusted or trusted, a more realistic threat model is that the foundries are legally and economically obliged to perform trustworthy service, and it is the individual employees that introduce security risks. We call the above as the trusted foundry and untrusted employee (TFUE) model. Based on this model,...
We present a design of a 2 to 12 port scalable multiport compiler with simultaneous read port access and closely packed graphics integration capability specially designed for low power high bandwidth, low latency stream vector processors and machine learning applications. Novel pipe-lined decoder and bitline repeater insertion helps to achieve a fast cycle time. Memory words can be accessed in different...
At the cross section of the fields of Uneven Terrain Navigation and Multi Agent Systems (MAS), in this work, a Detachable Compliant Modular Robot (DCMR) which can perform concurrent scene exploration by detaching into numerous parts, while preserving its ability to climb stairs is proposed and built. A spring is designed and used in the modular robot taking the worst-case-scenario of stairs encountered...
In recent research, it has been demonstrated that the pattern (or sequence) of memory access made to the server or external storage can leak very sensitive information even if the underlying data is encrypted. To mitigate this leakage, oblivious RAM (ORAM) has been proposed to provide provable security by hiding the access patterns. Ever since its introduction, substantial effort has been made to...
Emerging technologies such as Spin-transfer torque magnetic random-access memory (STT-MRAM) are considered potential candidates for implementing low-power, high density storage systems. The vulnerability of such nonvolatile memory (NVM) based cryptosystems to standard side-channel attacks must be thoroughly assessed before deploying them in practice. In this paper, we outline a generic Correlation...
Logic locking is a technique that has been proposed to thwart IC counterfeiting and overproduction by untrusted foundry. Recently, the security of logic locking is threatened by a new attack called SAT attack, which can effectively decipher the correct key of most logic locking techniques. In this paper, we propose a new technique called delay locking to enhance the security of existing logic locking...
In this paper, we propose a phase-driven Q-learning based dynamic reliability management (DRM) technique for multi-core processors to solve DRM problems of maximizing the processor performance subject to a large class of reliability constraints by turning ON/OFF cores and dynamic voltage frequency scaling. Our technique utilizes the existing methods to detect program phases (i.e. [17]) and learns...
Attacks on hardware can take on many forms. As modern chips are designed and fabricated in a global supply chain, circuit designs are subject to counterfeiting, piracy, and malicious modification by untrusted foundries, which are known as supply chain attacks. In this paper, we first survey existing circuit obfuscation techniques that are proposed to thwart the aforementioned attacks. Then, we investigate...
This paper presents a post-placement technique for through-silicon-via (TSV) induced thermal mechanical stress reduction. Thermal mechanical stress causes several critical failures such as material fracture (interfacial delamination and silicon substrate cracking) and TSV stress migration (SM). The von Mises stress is used as a material fracture metric. An analytical TSV SM model is used, which replaces...
The excessive heat accompanying high performance 3D ICs requires the use of aggressive cooling solutions such as interlayer micro-channels. However, interlayer micro-fluidic cooling comes with overheads such as conflict with through silicon vias (TSVs). Conventional approach which incorporates cooling after the design of the 3D system ([20]) could suffer significant overheads (e.g. substantially increasing...
Integrated micro-fluidic (MF) cooling is a promising technique to solve the thermal problems in 3D FPGAs [1] (As shown in Figure 1). However, this cooling method has some nonideal properties such as non-uniform heat removal capacity along the flow direction. Existing 3D FPGA placement and routing (P&R) tools are unaware of micro-fluidic cooling, thus leading to large on-chip temperature variation...
Recent work has shown that rising temperatures are increasing failures and reducing integrated circuit reliability. Although such results have prompted development of thermal management policies for stand-alone processors and on distributed power management, there is an overall lack of research on thermal management policies and their tradeoffs in sensor networks where sensors can overheat due to...
This paper presents a novel technique and algorithm for chip-scale electromigration (EM) aware 3D placement. A simple TSV's EM objective function is used, providing a computationally efficient way to represent TSV EM other than the finite-element-method (FEM) based simulation. Considering TSV's EM is mutually influenced by neighboring TSVs (due to TSV EM's dependence on TSV-induced thermal mechanical...
Face detection in still images and videos has been extensively studied over the last two decades. Attributed to the recent proliferation of cameras in consumer applications, research in face detection has gradually transformed into more unconstrained settings, with the goal of achieving performance close to humans. This presents two main challenges: (i) in addition to modeling the facial characteristics,...
Physical unclonable functions (PUFs) utilize manufacturing variations of circuit elements to produce unpredictable response to any challenge vector. The attack on PUF aims to predict the PUF response to all challenge vectors while only a small number of challenge-response pairs (CRPs) are known. The target PUFs in this paper include the Arbiter PUF (ArbPUF) and the Memristor Crossbar PUF (MXbarPUF)...
Recently, following the work pioneered by Kocher [1], using cache behavior as a timing side-channel to leak critical system information has received lots of attentions because of its easy-to-implement nature and amazingly good results. Recent attacks have been demonstrated to successfully leak the full key from many commonly used encryption algorithms including RSA, AES, etc. These attacks pose great...
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