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FinFET is one of the promising device architectures for sub-32 nm CMOS technology nodes. These non-planar devices benefit from near bulk-Si processing and improved control of short channels due to quasi gate-all-around operation. Their device operation is well studied and optimized in last half decade by various research groups. In this paper, we help evaluate the circuit potential of FinFETs by experimentally...
As a result of CMOS scaling, the critical dimension (CD) of integrated circuits has been shrinking. At sub-45 nm nodes, in which FinFET is a viable device architecture, line-edge roughness (LER) in current Si-based technologies forms a significant fraction of the line CD. In such cases, analyzing the impact of LER on FinFET performance is vital for meeting various device specifications. The impact...
Power and energy dissipation are increasingly important in SOC design. Low operating power reduces end-product costs by reducing the size of power supplies and heat sinks and by eliminating active cooling. Low SOC energy dissipation reduces battery size and increases battery life in portable equipment. As the use of multiple processors grows in SOC design, to gain the programmability and flexibility...
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