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A 12-bit Digital-analog converter (DAC) with pseudo Fibonacci sequence was fabricated in a 0.18μm CMOS technology. Proposed 12-bit DAC is composed of a 6-bit pseudo Fibonacci sequence and 6bit unary sequence. The power consumption of the proposed DAC is expected lower than that of conventional binary and unary DAC. The simulated power consumption of proposed 12-bit DAC is 40mV at 3.3V supply voltage...
A design of high linearity (IIP3), low flicker noise (NF), high conversion gain (CG) double-balanced Gilbert-cell mixer (DBGCM) is presented. Since the performance of a direct conversion receiver (DCR) is strongly affected by linearity and flicker noise (1/f) of a mixer in receiving side, a hybrid technique of dynamic current injection (DCI), a tuned inductor in switching pair and direct superposition...
This paper describes the design of 3.1 to 4.8 GHz CMOS power amplifier (PA) for ultra-wideband (UWB) applications using 0.18-μm CMOS technology. The UWB PA proposed here employs cascode topology with a current-reused technique to enhance the gain at the upper end of the desired band, an inter-stage inductor, and a resistive feedback at the second stage to obtain the flatness gain. The measurement...
This paper describes the design of a 3.1 to 4.8 GHz CMOS power amplifier (PA) for ultra-wideband (UWB) applications using TSMC 0.18-mum CMOS technology. The UWB PA proposed in this paper employs cascode topology with an additional common source stage to achieve high power gain. The current reused technique is implemented to enhance the gain at the upper end of the desired band for gain flatness and...
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