The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A new VLSI implementation for a finite field multiplier using reordered normal basis is presented. The hardware architecture uses domino logic building blocks as well as True Single Phase Clock (TSPC) flip-flops to achieve exceptional performance. The multiplier has been realized in a 0.18 μm CMOS process and can perform multiplication correctly up to a clock rate of 1.789 GHz, requiring 62048 μm2...
A new VLSI implementation for a 197-bit finite field multiplier using redundant representation is presented. The proposed design uses a simple module designed in domino logic as the main building block for the multiplier. We have used .18 mum CMOS technology from TSMC for our design. The final multiplier design was successfully simulated at a clock rate of 1.82 GHz. The proposed multiplier is at least...
Efficient implementation of the activation function is important in the hardware design of artificial neural networks. Sigmoid, and hyperbolic tangent sigmoid functions are the most widely used activation functions for this purpose. In this paper, we present a simple and efficient architecture for digital hardware implementation of the hyperbolic tangent sigmoid function. The proposed method employs...
In this paper, a high-speed word level finite field multiplier in F2m using redundant representation is proposed. For the class of fields that there exists a type I optimal normal basis, the new architecture has significantly higher speed compared to previously proposed architectures using either normal basis or redundant representation at the expense of moderately higher area complexity. One of...
The hyperbolic tangent function is commonly used as the activation function in artificial neural networks. In this work two different hardware implementations for the hyperbolic tangent function are proposed. Both methods are based on the approximation of the function rather than calculating it, since it has exponential nature. The first method uses a lookup table to approximate the function, while...
Reordered normal basis is a certain permutation of a type II optimal normal basis. In this paper, a high speed design of a word level finite field multiplier using reordered normal basis is presented. Proposed architecture has a very regular structure which makes it suitable for VLSI implementation. Architectural complexity comparison shows that the new architecture has smaller critical path delay...
A high performance finite field processor for elliptic curve cryptography is presented. One of the contributions in this work is the modified bit-parallel word-serial (BPWS) finite field multiplication algorithm and its corresponding pipeline-fashion multiplier architecture. The proposed multiplier achieves a throughput of one multiplication every N + 1 clock cycles, in contrast with at least N +...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.