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A new VLSI implementation for a finite field multiplier using reordered normal basis is presented. The hardware architecture uses domino logic building blocks as well as True Single Phase Clock (TSPC) flip-flops to achieve exceptional performance. The multiplier has been realized in a 0.18 μm CMOS process and can perform multiplication correctly up to a clock rate of 1.789 GHz, requiring 62048 μm2...
Efficient implementation of the activation function is important in the hardware design of artificial neural networks. Sigmoid, and hyperbolic tangent sigmoid functions are the most widely used activation functions for this purpose. In this paper, we present a simple and efficient architecture for digital hardware implementation of the hyperbolic tangent sigmoid function. The proposed method employs...
Reordered normal basis is a certain permutation of a type II optimal normal basis. In this paper, a high speed design of a word level finite field multiplier using reordered normal basis is presented. Proposed architecture has a very regular structure which makes it suitable for VLSI implementation. Architectural complexity comparison shows that the new architecture has smaller critical path delay...
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