The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Cu-Cu is a prefer choice of interconnects as it offered lower electrical resistance, no risk of shorting between the bump and higher reliability as compared to Cu-Solder Bump. However, Cu-Cu interconnect requests stringent condition such as Cu bump surface topography, flatness, uniformity of pillar array heights and clean bonding surface. From throughput point of view, Cu-Cu bonding is challenging...
Ultra-fine pitch (6μm) interconnects are essential for high-end application-products that demands high speed and high bandwidth inter-chip communication. Achieving Cu-Cu bonding with such a fine pitch is challenging since bond time is too long and bond interface gets easily oxidized. Throughput issue associated with long-bonding time is solved by using 2-step bonding procedure where first step is...
For ultra-fine pitch and high density Cu pillar low temperature bonding (200°C), the surface contact between substrate and Cu pillar array is the key. Therefore, the fabrication quality of copper bump array affects severely the bonding results. The qualitative factors include (1) Cu pillar array height uniformity, (2) free of copper oxide layer, (3) Cu material property (e.g. elastic modulus, grain...
Throughput issue is limiting the adoption of 3D IC stacking process although 3D IC has many advantages in shorter communication lines, lower electrical parasitic and lower package footprint. Local thermal compression bond on each chip stack incurs enormous process time if there is a need to have multi-chip stack and it will be further complicated with the enormous number of chip stack on one 12"...
Three dimensional (3D) IC integration technologies have become essential as the market demands for product with low power consumption, multi functions, smaller size and faster response have been increasing. 3D stacking with conventional high melting temperature solders such as SnAg and Sn may induce high thermal stress to the package. In this paper, chip to chip 3D stacking using no flow underfill...
Micro mirror packaging development for pico-projector application requires integration of magnets, silicon spacer and glass cap. A multilayer stack package has been designed for large deflection micro mirror. The magnets are used for electromagnetic actuation and are attached on either sides of the silicon beam by a pick and place machine. Different epoxy materials are evaluated to optimize the magnet...
A new D2W collective bonding approach is demonstrated with functional MEMS devices with smaller than 3 × 3 mm2 and 8 inch ASIC wafers. The new package design was proposed in order to reduce the parasitic effect by attaching the released MEMS dice directly to the pads on an ASIC wafer. Two different types of MEMS devices having combs structure and a beam structure were used in order to confirm the...
Low temperature bonding technology is developed using In-alloy on Au at a low temperature below 200??C forming robust intermetallics (IMC) joints with high re-melting temperature (>300??C), so that after bonding the IMC joints can withstand the subsequent processes without any degradation. Using similarly solder system and methodology, chips to wafer (C2W) bonding method has been developed, as...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.