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Before mass production, designed IC will be firstly verified using a Multi Project Wafer (MPW) procedure. How to package the MPW chips in a short time with a reasonable price is the common need of design houses. The Quad Flat Package (QFP) cavity carrier provides a “house” to protect the chips, and is strongly accepted by IC design companies and research parties. But usually, the QFP cavity carrier...
Head-in-Pillow (HiP) defect is a common issue in the Ball Grid Array (BGA) assembly. The defect is caused by several factors, individually or jointly, which includes warpage, misalignment, oxidation of the BGA ball, solder paste oxidation barrier capability, ect. The influence of before-reflow misalignment on HiP ratio(%HiP) has been studied. However, before-reflow misalignment can't describe HiP...
In this work, ball grid array (BGA) Sn-Pb solder joints on Co-P (4±0.5 at.%P and 8±0.8 at.%P) and Cu substrates were investigated to clarify the effects of interfacial reaction and morphology on the shear strength of the joints during thermal cycling. The interfacial intermetallic compounds (IMCs) in the solder joints were observed by back-scattered electron scanning electron microscopy. The composition...
Wafer bumping is a key process for flip chip packaging. There are several bumping techniques such as ball drop, electroplating and stencil printing, in which stencil printing is thought to be an economical choice because it is compatible with conventional SMT technology. However, when bump pitch is less than 100 μm, it becomes more difficult to control the deposition volume of the solder paste. In...
Wafer bumping is a key process for flip chip packaging. There are several bumping techniques such as ball drop, electroplating and stencil printing, in which stencil printing is thought to be an economical choice because it is compatible with conventional SMT technology. However, when bump pitch is less than 100 μm, it becomes more difficult to control the deposition volume of the solder paste. In...
Head-in-Pillow (HiP) defect is a common issue in the Ball Grid Array (BGA) assembly. The defect is caused by several factors, individually or jointly, which includes warpage, misalignment, oxidation of the BGA ball, solder paste oxidation barrier capability, ect. The influence of before-reflow misalignment on HiP ratio(%HiP) has been studied. However, before-reflow misalignment can't describe HiP...
In this work, ball grid array (BGA) Sn-Pb solder joints on Co-P (4±0.5 at.%P and 8±0.8 at.%P) and Cu substrates were investigated to clarify the effects of interfacial reaction and morphology on the shear strength of the joints during thermal cycling. The interfacial intermetallic compounds (IMCs) in the solder joints were observed by back-scattered electron scanning electron microscopy. The composition...
QFN (Quad Flat No-lead) packages become popular in recent years because they provide many advantages over conventional leadframe packages. Due to CTE (Coefficient of Thermal Expansion) mismatch of different materials applied in the package, significant warpage will be generated during QFN packaging process, and may cause yield and reliability issues. In this paper, the warpage of a QFN strip induced...
Epoxy Molding Compound (EMC) is the encapsulation material that can provide mechanical support and protection to IC packages. In the meantime, it is also a key contributor to package warpage. Finite element analysis (FEA) has been widely used in packaging development to improve product performance more efficiently. EMC is usually modeled as piecewise linear elastic material in FEA model for simplification...
SIM cards have been more and more widely used and the failure of packaging becomes a remarkable issue. In this paper, effects of die thickness and layout, material properties and packaging process parameters on the stress of dies were analyzed based on finite element simulation. The whole simulation includes two main packaging processes: cooling after die attach and molding process. The warpage of...
The solder ball pitch of BGA packages in mass production now is normally above 0.5 mm. To fulfill the future demand of package miniaturization, the 0.4 mm ultra fine pitch BGA solder joint was researched in this paper. The solder volume shrinkage along with the ball pitch decrease was found to affect the joint microstructure, which could be characterized in two aspects: the Sn dendrites in bulk solder...
Wafer level packaging (WLP) technology has been used to integrate high-Q inductor on Si substrate. These inductors consist of a thick Cu electroplated rerouting to reduce series resistance and a thick dielectric layer to separate the inductors from Si substrate. The measured results show that the peak O-factor is 30 at 4 GHz for a 0.77 nH inductor, which is good agreement with the simulated performance...
The solder joints reliability of electronic packages during board level drop impact is a great concern for semiconductor manufacturers. Many researchers have adopted numerical simulation to investigate the drop performance of electronic package because it is fast and cost-effective. However, the solder balls, which are recognized as vital parts for the integrity of solder joints and the overall function...
Different metallization systems and bonding designs of Ag-Sn bonding were investigated to achieve good bonding. The bonding strength was evaluated by shear force. The microstructure of bonding interface was inspected by scanning electronic microscopy and ED AX. Shear force test was performed for as-bonded dice. The test results indicate differences among different metallization systems. The bonding...
Wafer bonding technology is important for most MEMS devices' packaging, especially for RF-MEMS devices. Different materials systems, such as Au-Sn, Au-In, have been developed for wafer bonding. A new bonding system, using Ag-Sn, is investigated in this paper. Comparing to well developed Au-Sn bonding (typically bonding temperature of 280degC ), Ag-Sn would provide a potentially lower temperature,...
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