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Providing low-latency and high-throughput is an important design feature of an I/O scheduler. Especially, when multiple applications share and compete for a storage resource, the operating system is required to schedule the IO requests for the maximum throughput. Recently, the flash-based storage, solid-state drive (SSD) has been popularly used in various computing systems and traditional scheduling...
MicroRNA maturation is initiated by RNase III DROSHA that cleaves the stem loop of primary microRNA. DROSHA functions together with its cofactor DGCR8 in a heterotrimeric complex known as Microprocessor. Here, we report the X-ray structure of DROSHA in complex with the C-terminal helix of DGCR8. We find that DROSHA contains two DGCR8-binding sites, one on each RNase III domain (RIIID), which mediate...
Controlling the latency and throughput is a crucial part of designing an I/O scheduler that can provide guaranteed quality-of-service of a shared storage resource to multiple competing applications. Previously proposed I/O schedulers have mainly focused on ensuring proportional bandwidth allocation and a user-defined latency. However, the algorithms are not optimized for high-speed storage with restricted...
Argonaute is a key enzyme of various RNA silencing pathways. We use single-molecule fluorescence measurements to characterize the reaction mechanisms of the core-RISC (RNA-induced silencing complex) composed of human Argonaute 2 and a small RNA. We found that target binding of core-RISC starts at the seed region, resulting in four distinct reaction pathways: target cleavage, transient binding, stable...
MicroRNA (miRNA) maturation is initiated by Microprocessor composed of RNase III DROSHA and its cofactor DGCR8, whose fidelity is critical for generation of functional miRNAs. To understand how Microprocessor recognizes pri-miRNAs, we here reconstitute human Microprocessor with purified recombinant proteins. We find that Microprocessor is an ∼364 kDa heterotrimeric complex of one DROSHA and two DGCR8...
The MapReduce frameworks using a modern graphic processor (GPU) have improved the performance of data-intensive applications. While the prior researches have enhanced the parallelism of the MapReduce application on a GPU, archiving optimal distribution of big data on heterogeneous devices is still a challengeable issue. We therefore propose a method to evenly separate the computing cost under limited...
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