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The 2×2 wireless LAN (WLAN) + Bluetooth (BT) combo chip continues to be the most versatile product category in the wireless connectivity space. It finds usage in a wide range of applications, such as laptops, tablets, high-end smartphones, gaming consoles, set-top boxes, wireless routers and in-car/personal hot-spot devices. Digital-intensive SoCs have been relying on Moore's law to keep the cost...
High-performance phase-locked-loops (PLLs) are key building blocks for many modern ICs. The sub-sampling PLL proposed in [1] uses a reference clock REF to sample a high-frequency VCO and converts phase/timing error into voltage. The steep dv/dt slope of the VCO helps to realize a high phase-detection gain and greatly suppresses the noise of loop components succeeding the phase detector, leading to...
The fast adaptation of WiFi 802.11ac 256-QAM mode requires RF clocks with very low integrated phase error to deliver good EVM performance. On the other hand, smaller area and lower power are always desired for lower cost and longer battery life. This work presents a 28nm CMOS LO design for dual-band 802.11abgn/ac radio with overall architecture shown in Fig. 9.4.1. It addresses the aforementioned...
Digital intensive architectures allow for flexibly programmable frequency synthesis. Timing jitter and/or phase noise is an important quality criterion for synthesizers. This paper reviews fundamental limitations for jitter in digital frequency architectures, aiming at finding a basis to compare alternative architectures and optimize jitter performance. It motivates why the product of jitter variance...
As the latest product of Godson processor series, the Godson-3B processor is an 8-core high-performance general-purpose processor implemented in 65nm CMOS low-power general-purpose mixed process with 7 layers of Cu metallization. Godson-3B contains 582.6M transistors (including 4MB L2-cache) within 299.8mm2 area. The number of signal pins in Godson-3B is 654. The highest frequency of Godson-3B is...
A divider-less PLL exploits a phase detector that directly samples the VCO with a reference clock. No VCO sampling buffer is used while dummy samplers keep the VCO spur <;-56dBc. A modified inverter with low short-circuit current acts as a power efficient reference clock buffer. The 2.2 GHz PLL in 0.18 μm CMOS achieves -125dBc/Hz in-band phase noise with only 700 μW loop-components power.
In this paper, an optimum stage ratio (tapering factor) for a tapered CMOS inverter chain is derived to minimize the product of power dissipation and jitter variance due to device mismatch. Analysis shows that this optimum stage ratio (2.4) is lower than that of minimum delay (3.6) and minimum power-delay (6.35) product. This analysis is verified by simulation results using standard 180 nm as well...
This paper presents a 2.2 GHz clock-generation PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. The PLL does not need frequency divider in locked state and achieves a low in-band phase noise values at low power.
This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and...
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