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in shared-memory Chip Multiprocessor (CMP), shared data between different cores must be exchanged through the last-level-shared-cache and cache coherence must be maintained at the same time. As the number of cores increase, the cache coherence wall has become more and more serious. As for the multimedia applications full of streaming-like data, existing multicore cache coherence protocols show lower...
A??@rate-distortion optimal rate control algorithm based ??I-domain for Video Coding is presented, which improves the existing rate model based ??I-domain and distortion model. It uses Lagrange optimization method and obtains optimization quantization parameter for video encoder. Experimental results show that the rate control algorithm can achieve better video quality than JM98's. The algorithm is...
With the advent of chip multiprocessor (CMP) architecture, programmer must tune the program to the architecture in order to fully utilize the hardware resource. How to parallel program multimedia application in the CMP is a big obstacle. In this paper, we introduce the potential parallelism in the multimedia application and the multi-grain parallelism architecture in the CMP; also we make a systematic...
An embedded processor with SIMD extension is presented. The processor contains 32-bit dual-issue RISC core with out-of order execution capability. A dedicated short-vector SIMD unit is extended to speed up the multimedia processing. Also an effective co-verification method is designed to verify the processor. It focuses on the architecture design and the verification of the embedded processor. The...
Memory system of chip multi-threaded processors (CMT) suffers greater than ever before because of memory latencies brought by overloaded memory accessing requests. Data prefetching using helper threads has been proved to be an effective approach to tolerate memory latencies by past researches. However, as the sum total of threads increase, simultaneously occupying available idle thread context in...
The pre-sending technique, proposed from distributed shared memory systems, pushes data to cache instead of pulling,aiming at reducing the traffic of communication. On a purpose of effectively improving cache hit ratio, this paper proposes a hardware-based active-pushing technique, which directs data owners like lower-level of memory hierarchy to actively push the predicted data at the right moment...
One 32-bit RISC processor for embedded application is presented. With respect to the limitation of power and area in the embedded system, the RISC processor is deliberately designed. Dual-issue technology is adopted to improve the performance; the complex logic of the dynamic scheduling algorithm is allocated into different pipeline stage to improve the frequency. Lower power design method is used...
In SMT architecture, instruction fetch unit is capable of fetching instructions from one or more threads simultaneously. Because of resource competing and run-time characteristics of threads, system resources are not sufficiently utilized. Considering necessary factors, a powerful instruction fetch mechanism can alleviate the adverse effects through appropriately fetch as many compatible instructions...
To satisfy the increasing applications of the electrospun nanofibers, a novel method for the high throughput nanofibers electrospinning which is called "Needleless ElectroSpinning (NES)" is presented in the article. Instead of using the conventional needle, ElectroHydroDynamics (EHD) instabilities mechanism on the electrified liquid film free surface forms the foundation of the NES process,...
To speed up the processing of the multimedia data, an independent multimedia process unit can be integrated into the embedded processor by SOC technology. Based on one existing embedded processor, the authors design the IP core of the multimedia process unit of the processor. The IP can process two multimedia instructions per cycle. It has six pipeline stages. The complex logic of the dynamic scheduling...
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