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This paper proposes an on-chip differential transmission line interconnect using a pre-emphasis technique for high-speed onchip signaling. The new transmitter with dynamic output-impedance control for pre-distortion of signals is presented. Simulation results showed that the proposed interconnect in 90 nm Si CMOS has possibilities of over-20-Gbps signaling and better energy-per-bit performances than...
This paper proposes a high energy-efficient pulsed-current-mode transmission line interconnect (PTLI) for on-chip networks. The stacked-switch transmitter (Tx) is introduced for saving a static power of Tx. Point-to-point and multi-drop PTLIs are demonstrated, and simulation results show that the 5-mm-long PTLI with six Txs and six receivers (Rxs) can achieve multi-drop signaling. The point-to-point...
This paper proposes a low-power on-chip transmission line interconnect (TLI) using wafer level package (WLP) technology. A 0.18 mum Si CMOS process was used to fabricate a transmitter (Tx) and a receiver (Rx). The prototype TLI with a transmission line in WLP has about 40% smaller power consumption than that with a transmission line in multilevel interconnects.
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