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This paper presents two novel architectures for two-dimensional (2-D) Haar wavelet transform (HWT) of transform block in face recognition systems. The proposed architectures comprises 2-D HWT with transpose-based computation and dynamic partial reconfiguration (DPR) that have been synthesised using VHDL and implemented on Xilinx Virtex-5 FPGAs. To evaluate the proposed architecture, comparison for...
This paper presents the design and implementation of finite Radon transform (FRAT) on field programmable gate array (FPGA). To improve the implementation time, Xilinx AccelDSP, a software for generating hardware description language (HDL) from a high-level MATLAB description has been used. FPGA-based architectures with three design strategies have been proposed: direct implementation of pseudo-code...
In this research, novel architectures based on different design approaches and arithmetic techniques such as direct mapping implementation, dynamic partial reconfiguration (DPR) mechanism, distributed arithmetic (DA) and systolic array (SA) will be developed for three dimensional (3D) medical image compression system. Moreover, solutions for processing large medical volumes will be investigated and...
This paper describes the design and implementation of 3D Haar wavelet transform (HWT) with transpose based computation and dynamic partial reconfiguration (DPR). As a result of the separability property of the multi-dimensional HWT, the proposed architecture has been implemented using a cascade of three N-point 1D HWT and two transpose memory for a 3D volume of N ?? N ?? N, suitable for 3D medical...
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