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This paper proposes a novel circuit architecture and its operation style for three-level ferroelectric random access memory (FeRAM) which can improve storage density by 1.5 times compared to traditional ITIC FeRAM under same technology. A new reference voltage generation scheme is adopted to enhance the reliability of this proposed circuit architecture. Based on the results of simulation, the function...
This study analyzed the effect on the bit-line voltage of imprint degradation in FeRAM. The hysteresis loop of the ferroelectric capacitor fitted by the three-line piecewise linear approximation model is proposed here to establish the relationship between bit-line voltage and imprint. Formulas are derived from this model for approximately calculation of the variation of bit-line voltage along with...
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