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This paper proposes an on-chip differential transmission line interconnect using a pre-emphasis technique for high-speed onchip signaling. The new transmitter with dynamic output-impedance control for pre-distortion of signals is presented. Simulation results showed that the proposed interconnect in 90 nm Si CMOS has possibilities of over-20-Gbps signaling and better energy-per-bit performances than...
This paper proposes a low-power on-chip transmission line interconnect (TLI) using wafer level package (WLP) technology. A 0.18 mum Si CMOS process was used to fabricate a transmitter (Tx) and a receiver (Rx). The prototype TLI with a transmission line in WLP has about 40% smaller power consumption than that with a transmission line in multilevel interconnects.
Hierarchical power distribution with a power tree has been developed. The key features are power tree management rules and a distributed common power-domain implementation. The hierarchical power distribution supports a fine-grained power gating with dozens of power domains, which is analogous to a fine-grained clock gating. Leakage currents of a 1,000,000-gate power domain were effectively reduced...
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