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The paper presents an overview of the Bias Temperature Instabilities (BTI) reliability in High-k/Metal gate technologies. We show that mobility performance and NBTI reliability are strongly correlated and that they are affected by the diffusion of nitrogen species N at the Si interface. PBTI, more sensitive to bulk oxide traps, is strongly reduced in very thin dielectric films. Reducing the metal...
In this work we present the integration of Band Engineered TANOS-like memories using HfSiON in the tunnel stack to boost the programming efficiency and improve cycling. An accurate correlation analysis between the gate-stack material physical properties and the memory performances is presented. In particular, the importance of the nitridation step of HfSiON on the memory retention characteristics...
In this work, memory devices integrating a double layer of silicon nanocrystals as trapping medium and a high-k HfAlO-based control dielectric are presented. We will show that the use of two stacked Si-nc layers significantly improves the memory window compared to the single Si-nc layer devices, without introducing dispersions on the charging dynamics. Then, we also evaluate the potentiality of hybrid...
The goal of this work is to give a clear physical comprehension of the charge loss mechanisms of SANOS (Si/Al2O3/Si3N4/SiO2/Si) memories. Retention at room and high temperature is investigated on different samples through experiments and theoretical modeling. We argue that at room temperature, the charge loss essentially results from the tunneling of the electrons trapped at the nitride interface,...
In this work, we present an experimental and theoretical study of nitride trap devices with a HTO/Al2O3 bi-layer blocking oxide. Such SAONOS (Silicon/Alumina/HTO/Nitride/Oxide/Silicon) devices are compared with standard SONOS (Silicon/HTO/Nitride/Oxide/Silicon) and SANOS (Silicon/Alumina/Nitride/Oxide/Silicon) memories. The role of the different layers (blocking oxide and control gate) is deeply analyzed,...
A systematic study of mobility performances and BTI reliability was done in advanced dielectrics stacks. By reducing the oxide films thicknesses THKles2.5 nm, PBTI becomes generally very low and associated lifetimes are always over 10 years. By studying a large variety of dielectric stacks we also clearly demonstrate that mobility performances, interface defects Nit and NBTI reliability are strongly...
The integration of silicon nanocrystal (Si-nc) nonvolatile memory (NVM) arrays with HfAlOx based interpoly dielectric (IPD) is presented for the first time. The data obtained on array vehicles programmed in Fowler-Nordheim operation regime are in excellent agreement with previously presented results on single cells, as well as theoretical data and allow the evaluation of the scalability of the Si-nc...
In this paper we show for the 1st time that Silicon nanocrystal (Si-ncs) memories with high-k (HfO2, Al2O3 and HfAlO) interpoly dielectrics (IPD) can offer excellent behaviour in the Fowler-Nordheim regime, with great relevance for future sub-45 nm NAND memory generations. We significantly advance the state-of-the-art by showing a strict correlation between the different IPD properties and the performance...
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