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This paper presents a sensor node processor (SNP) with optimized energy efficiency and performance for intelligent sensing through architecture-level optimization and ultra-low voltage operation with timing-error monitoring. Two typical intelligent sensing applications are demonstrated with the proposed processor, consuming 39 and 29pJ/cycle at 0.5V respectively.
A new model and a theory to capture the effects of halo (pocket) implants on the flicker noise of the advanced-node MOSFETs have been proposed and verified with measurements. The model can accurately capture the bias dependence of the drain-current flicker-noise (FN) power density. Also for the first time, we explain and model the unexpected channel-length dependence of FN power density in strong-halo...
A 4-channel Vertical Cavity Surface Emitting Laser (VCSEL) driver array is designed in a 0.18μm CMOS technology. Simulated results show that each channel works at 10Gb/s (12.5Gb/s max) under a supply voltage of 1.8 V. Thus, aggregated total capacity of 40 Gb/s can be obtained from 4 channels. The power dissipation of each channel is only 50mW. To decrease the fall time of the output waveform, C3A...
In this paper, a fully integrated low voltage charge pump for thermoelectric energy harvesters is presented. The proposed dual-mode architecture achieves both the low startup voltage in a startup mode and high conversion efficiency in a normal operation mode without off-chip inductors and capacitors. In the measurement, the proposed circuit successfully converts 120-mV input to 770-mV output with...
A fifth-order CMOS Gm-C Chebyshev low-pass filter with a tunable cutoff frequency of 5-80 MHz is presented. A phase-locked loop (PLL) frequency synthesizer control system automatically references the frequency response of the filter to an external fixed clock frequency. Spectre simulation results of the 1.8-V filter in a 0.18-µm CMOS process show that the cutoff frequency varies by less than 1 percent...
To effectively reduce output ripple of switched-capacitor DC-DC converters which generate variable output voltages, a novel feedback control scheme is presented. The proposed scheme uses pulse density and width modulation (PDWM) to reduce the output ripple with low output voltage. The prototype chip was implemented using 65nm CMOS process. The switched-capacitor DC-DC converter has 0.2-V to 0.47-V...
In this paper, a 0.18-V input three-stage charge pump circuit applying forward body bias is proposed. In the developed charge pump, all the MOSFETs are forward body biased by using the inter-stage/output voltages. By applying the proposed charge pump as the startup in the boost converter, the lower kick-up input voltage of the boost converter can be achieved. To verify the circuit characteristics,...
Digital LDO is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65nm CMOS achieved the...
In this research work the design and prototyping of novel planar microelectrode arrays that utilize SU-8 as the insulating material is presented. The microelectrode arrays are fabricated as a key component of an extracellular neural recording system comprising a full customized CMOS analog neural signal readout ASIC for neural signal processing and an 8 by 8 microelectrode array for acquiring the...
In this paper we present the design and prototyping of a 24-channel mixed signal full-customized CMOS integrated biosensor chip for in vitro extracellular recording of neural signals. Design and implementation of hierarchical modules including microelectrode electrophysiological sensors, analog signal buffers, high gain amplifier and control/interface units are presented in detail. The prototype chip...
In this paper we present a full-customized CMOS biosensor integrated circuit (IC) design, layout, and implementation techniques for extracellular multichannel action potential recording applications. Schematics and simulation data for each of the sub-circuit macros are presented which includes contact sensors, unity gain buffer, variable gain amplifier and logic control unit. The chip provides a satisfactory...
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