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This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). To reduce power and area, the monotonic switching procedure is combined with a parasitic-compensated split-capacitor DAC that also has an improved capacitor matching. The nonlinearity of the conventional split-capacitor DAC due to parasitic capacitance and capacitor mismatch is...
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