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Many current source models (CSMs) have been proposed for the gate-level circuit analysis and timing analysis for sub-90-nm CMOS designs during the past decade. However, most of them may suffer from large delay errors for multiple-stages of combinational logic gates. This paper presents an extended CSM which can provide high accuracy in both single-stage and multiple-stage combinational logic gates...
Crosstalk noise is a critical issue in the deep submicron circuit design, since it causes functional failures in IC chips. This paper proposes an efficient approach to find the timing region of the circuit that timing failure occurs in an IC chip. The proposed method efficiently finds timing failure region by using CGOV metric without iterative simulations. In the experimental results, the proposed...
This paper proposes an efficient load model for power network noise analysis. The proposed method approximates an uninteresting part of a large mesh-structured circuit to a simple load model which consists of a couple of RLC elements. In the experimental results, the proposed method reduced a CPU time of SPICE simulation by up to 95% while suppressing the maximum and average voltage errors less than...
The Monte-Carlo simulation based leakage current analysis provides very accurate results, but it has high computational complexity. In this paper, we present the Monte-Carlo based leakage estimation method, which is implemented on a GPU and a CUDA platform. Thereby using the Monte-Carlo method on a GPU, we can expect not only high simulation accuracy but also high estimation efficiency. Because a...
This paper proposes an efficient reduction technique dedicated to a resistive mesh structured power network. The proposed method reduces an uninterested partition of a large mesh structured circuit, which the partition does not contain storage elements, to a simple circuit which consists of resistors and current sources only. The proposed method provides the upper bound of the maximum error of port...
Moving to deeper in the ultra-deep sub-micron (UDSM) era continuously increases process variation. Although reliable timing analysis is necessary to ensure quality design, the increase of process variation tends to degrade the validity of the worst-case corner (WC) timing analysis. In this paper, we investigate the validity of WC timing analysis, as compared to statistical static timing analysis,...
In this paper, we analyzes the error due to the effects of local random variation on delay and leakage in the gate level statistical modeling. In experiments with various gates, without considering the local random variation showed over 20% of maximum error on the gate delay standard deviation, when compared with the results considering the local random variation. Moreover, in the aspect of leakage,...
Incremental analysis is indispensible for efficient circuit optimization, as it analyzes the effect by the modified circuit part only instead of analyzing a whole circuit again from beginning. This paper presents a new incremental statistical static timing analysis (SSTA) method, called timing yield-based incremental analysis (TYIA). TYIA uses the probability that the gate timing slack is non-negative...
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