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An energy-efficient nonvolatile intelligent processor (NIP) is proposed for battery-less energy harvesting system. This NIP employs RRAM-based nonvolatile logics (NVL) with self-write-termination (SWT) scheme and low-power processing-in-memory (PIM) to achieve energy-efficient computing against frequent power-off situations. An NIP test chip was fabricated in 150nm CMOS process using HfO RRAM. This...
Recent embedded ReRAM has a small resistance-ratio (R-ratio), which results in a small read sensing margin (ISM). A larger BL current (IBL) increases the input offset (IOS) of current-mode sense amplifiers (CSA), resulting in low-yield read operations and long read access times (TCD). This work proposes an IBL-aware small-IOS CSA, using a dynamic trip-point-mismatch sampling (DTPMS) scheme to increase...
Energy harvesting is under intense investigation as a promising substitute for batteries. However, given the erratic nature of ambient energy sources, temporary status in conventional CMOS circuits can be lost upon a sudden power outage. Taking advantage of emerging nonvolatile memories (NVMs), nonvolatile processor (NVP) backs up system contexts when power failure occurs, and recalls pre-stored data...
Many search engines or filters for the internet-of-things and big-data employ ternary content-addressable-memory (TCAM) to suppress power consumption in the transmission of data between end-devices and servers. Nonvolatile TCAMs (nvTCAM) are designed to achieve zero standby power with smaller area overhead and faster power off/on operations than those found in conventional TCAM+NVM 2-macro schemes...
Ternary content-addressable memory (TCAM) is used in search engines for network and big-data processing [1]–[6]. Nonvolatile TCAM (nvTCAM) was developed to reduce cell area (A), search energy (ES), and standby power beyond what can be achieved using SRAM-based TCAM (sTCAM) [1]–[2]: particularly in applications with long idle times and frequent-search-few-write operations. nvTCAMs were previously designed...
Many big-data (BD) processors reduce power consumption by employing ternary content-addressable-memory (TCAM) [1-2] with pre-stored signature patterns as filters to reduce the amount of data sent for processing in the following stage (i.e., wireless transmission). To further reduce standby power, BD-processors commonly use nonvolatile memory (NVM) to back up the signature patterns of SRAM-based TCAM...
This study proposes an RC-filtered stress-decoupled (RCSD) 4T2R nonvolatile TCAM (nvTCAM) to 1) suppress match-line (ML) leakage current from match cells (IML-M), 2) reduce ML parasitic load (CML), 3) decouple NVM-stress from wordlength (WDL) and IML-MIS. RCSD reduces NVM-stress by 7+x, and achieves a 4+x improvement in speed-WDL-capacity-product. A 128×32b RCSD nvTCAM macro was fabricated using HfO...
This work demonstrates a 3D vertical-gate (3DVG) NAND Flash with circuit-level techniques to overcome degradations in speed, yield, and reliability resulting from cross-layer process variations. The key enables include: (1) layer-aware program-verify-and-read (LA-PV&R), (2) layer-aware-bitline-precharge (LA-BP), and (3) a wave-propagation (WP) fail-bit detection (FBD) scheme. A fabricated 2-layer...
This work proposes an 8T cell with dual data-aware write-assist (D2AW) and negative read-WL (NRWL) schemes to increase the figure of merit (FOM): [cell stability (CS)*cycle frequency (f)]/[cell area (A)*minimum VDD (VDDmin)]. The column-based D2AW provides, for the first time, the solution to the trade-off between the row/column half-select (HS)-CS margins and the write margin (WM) thanks to the dual...
Eight-transistor (8T) dual-port static random access memory (DP-SRAM) suffers from read and write disturbances at low voltages when both ports are accessed simultaneously, and write disturbance dominates the VDDmin in high-speed applications. This brief proposes a write-assist 8T (WA8T) cell to suppress the write disturbance for DP-SRAM to achieve a lower VDDmin with low area overhead and power consumption...
Low supply voltage is a commonly method for suppressing system power consumption and thermal effects, improving battery life and chip reliability for mobile SoC and 3D-IC devices. This paper describes various mainstream and emerging embedded non-volatile memory (eNVM) solutions for mobile SoC and 3D-IC designs. This study also reviews and discusses the key circuit technologies for decreasing the VDDmin...
A differential data aware power supplied (D2AP) 8T-SRAM cell has been proposed to address the stability trade-off-issues between write and half-select accesses that still remain in the conventional 8T and 6T cells. Powered by its bitline pair, this 8T cell applies differential data-aware-supplied voltages to its cross-coupled inverters to enlarge both stability margins for write and half-select accesses...
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