The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We investigated bias temperature instability (BTI) and time dependent dielectric breakdown (TDDB) in TaCx/HfSiON MOSFETs in terms of the effects of TaCx metal gate electrode, using various Ta composition and TaCx thickness. We find a dual nature of TaCx metal gate electrode effects on the reliability. The gate electrode has both positive and negative influence on BTI and TDDB. Though various TaCx...
We present a systematic examination of Vth controllability using Y2O3, La2O3, and MgO2 layers by atomic-layer-deposition (ALD) technology with HfSiON/TaSiN gate first stacks for half-pitch (hp) 32 nm-node metal gated bulk devices. By employing base-Y2O3 layers of 1 mono-layer (ML< 0.5 nm), ultra-thin equivalent-oxide-thickness (EOT: 0.72 nm) can be achieved with excellent Vth controllability (|DeltaV...
Practical and manufacturable solutions for metal gate/dual high-k CMOS integration are presented. In order to overcome the difficulties of threshold voltage control of metal gate/high-k gate stack especially for gate-first integration, several material designs have been proposed so far. These include different metal gate materials and different high-k materials which are separately used in nMOS and...
We report TaCx/HfSiON gate stack CMOS device with simplified gate 1st process from the viewpoints of fixed charge generation and its impact on the device performance. Moderate Metal Gate / High-K dielectric (MG/HK) interface reaction is found to be a dominant factor to improve device performance. By optimizing TaCx composition, fixed charge free TaCx/HfSiON device is successfully fabricated. Also,...
Low Vth HfSiON/TaSiN gate first stacks have been demonstrated, using atomic-layer-deposition (ALD) La2O3 cap layers, for half-pitch (hp) 32 nm-node metal gated bulk devices. By employing a very slow ALD-La2O3 growth rate (0.036 nm/cycle) within 30 cycles, the smallest equivalent oxide thickness (EOT< 0.7 nm) can be achieved with high electron carrier mobility and excellent Vth control (Vth<...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.