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An on-chip automatic erase technique using an internal voltage generator has been developed and has proved to operate well in 1-Mb-flash EEPROM. This technology permits accurate control of erasure and guarantees the performance after erasure of the true single-transistor-per-cell type of flash EEPROM. Device implementation is described
An 8-ns serial access time has been realized in a 4-Mb static RAM with newly proposed circuits (hierarchical shift registers and look-ahead circuits) which can access up to 4 Mb. This memory realizes a 125-MHz fast serial READ/WRITE operation suitable for ultra-high-speed memory systems such as image-processing systems, high-speed testing systems, and supercomputers. This function is also beneficial...
An internal erase and erase-verify control system implemented in all electrically erasable, reprogrammable, 80-ns, 1-Mb flash memory suitable for in-system reprogram applications is discussed. This system features a command signal latch, a sequence controller, and a verify voltage generator. Timing in the electrical erase mode is shown. The erase mode is initiated by a 50-ns pulse. An erase and erase-verify...
A 55-ns, 4-Mb (256-kW*16 b) EPROM with a 1-s programming time is described. By use of 0.8- mu m lithography, a memory cell size of 2.8*2.8 mu m/sup 2/ is achieved, resulting in an 8.13*9.27 mm-die. A polycide structure is used to decrease the word line resistance and interconnection resistance, and a lightly doped drain (LDD) structure is used in the peripheral gates of pMOS and nMOS transistors to...
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