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Content-Centric Networking (CCN) proposals rethink the communication model around named data. In-network caching and multipath routing are regarded as two fundamental features to distinguish the CCN from the current host-centric IP network. In this paper, we tackle the problem of joint collaborative caching and multipath routing in CCN. We achieve this with an online and offline combination caching...
Recent asynchronous VLSI circuit placement approach tries to leverage synchronous placement tools as much as possible by manual loop-breaking and creation of virtual clocks. However, this approach produces an exponential number of explicit timing constraints which is beyond the ability of synchronous placement tools to handle. Thus, synchronous placer can only produce suboptimal results. Also, it...
IPv6 is widely deployed in recent years, but IPv6 protocols still have many security threats, especially the traffic hijack in LAN (Local Area Network). In this paper we implement an IPv6 traffic hijack test system to help user aware the security risks, and then design a defense tool using DNSSEC to avoid traffic hijack attack.
In this paper, we present a new erase gate disturb mechanism during programming of selected cell for split-gate Flash memory. This type of disturb occurs on the programmed cell sharing the same erase gate as the selected cell. The disturb is due to electron-loss from floating gate to erase gate caused by low-field Fowler-Norheim (F-N) tunneling. We proposed a method that adds extra bias voltages at...
In this paper, we propose a novel min cut based algorithm for multiple supply voltage assignment under timing constraints. Different with the traditional sensitivity based methods which focus on how to make full use of the slacks of non-critical gates, the proposed algorithm concentrates on critical gates. The circuit is initialized in the lowest power level, then the length of critical paths is tried...
Low power design has become one of the most significant requirements when CMOS technology entered the nanometer era. Therefore, timing budget is often performed to slow down as many components as possible so that timing slacks can be applied to reduce the power consumption while maintaining the performance of the whole design. Retiming is a procedure that involves the relocation of flip-flops (FFs)...
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