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As data rate increases, crosstalk becomes a significant source of high jitter. Although many techniques have been investigated to reduce crosstalk, it is not possible to fully eliminate coupling. In particular, near-end coupling between transmitter (TX) to receiver (RX) occurs at the interface of chip and PCB is one of the main sources of crosstalk. This TX to RX coupling is detrimental compared to...
With silicon process technology advanced to 20 nm node and beyond, die size is continuously shrinking. Package cost is very sensitive to the total cost of an entire chip/ASIC (Application-Specific Integrated Circuit). To reduce package cost, either the package layer count needs to be reduced or the package size needs to be decreased. For a given chip/ASIC design, its high-speed IO (Input Output) pin...
This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling and correlation for PCBs (Printed Circuit Boards) with FR4 substrate materials. The entire channel under investigation includes two packages, a 21-layer ceramic and a 12-layer organic, and a 22-layer PCB. A probing station, microprobes and a VNA are used to measure the entire channel S-parameters and...
A parallel FDTD algorithm has been realized based on 1-D domain decomposition. Data communication among different adjacent processors is manipulated by a self-defined C++ class ( MPI_FDTD) in which portable functions of the message passing interface (MPI) library are used. The details of the implementation are discussed. EMC applications of the code such as cross talk of traces, cavity, vias, as well...
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