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Two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper. The first feature is the integration of stress-enhancement techniques with the dual metal-gate + high-k transistors. The second feature is the extension of 193 nm dry lithography to the 45 nm technology node pitches. Use of these features has enabled industry-leading...
This paper describes the fabrication and performance of uniaxial strained silicon CMOS transistors with NiSi metal gate electrodes and ultra-thin 1.2nm gate oxide. This work offers the first comprehensive evaluation of Si CMOS devices integrating NiSi metal gate (FUSI) process with highly strained Si channels. Performance gains from FUSI gate stack and uniaxial strained Si channels are demonstrated...
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