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This paper describes the effect of thickening Au-plated ohmic electrodes in AlGaN/GaN HEMTs on the drain current and on-resistance. By increasing the thickness of Au-plated ohmic electrodes up to 5 µm, the fabricated AlGaN/GaN HEMT with a total gate width from 2 to 10 mm exhibited an increase in the maximum drain current by about 50 % and a reduction in the on-resistance by more than 40 %.
In this paper we have investigated the relationship between off-state breakdown voltage and gate-to-drain distance (Lgd) for AlGaN/GaN HEMTs fabricated on a free-standing GaN substrate. The off-state breakdown voltage exhibited a linear increase up to Lgd of around 80 µm but saturated at about 4000 V when Lgd > 80 µm. Therefore, we proposed that when Lgd < 80 µm, the breakdown voltage of HEMTs...
A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4th generation high-k metal gate, and 6th-generation strained silicon, resulting...
We describe the dependence of annealing temperature on the ohmic contact resistance for n-type GaN layers having ohmic metal stacks of V/Al/Mo/Au and Ti/Al/Mo/Au. Measurement results indicated that the contact resistance for V/Al/Mo/Au with a doping level of 2×1018 cm−3 was 0.35 Ωmm after annealing at 600 °C, while that for Ti/Al/Mo/Au did not show good ohmic behaviors after annealing below 650 °C...
A 32 nm logic technology for high performance microprocessors is described. 2nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32 nm or 28 nm logic technology. NMOS drive currents are 1.62 mA/um Idsat and 0.231 mA/um Idlin at 1.0 V and 100 nA/um Ioff. PMOS drive currents are 1.37 mA/um Idsat and 0.240 mA/um Idlin at 1.0 V and 100...
Two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper. The first feature is the integration of stress-enhancement techniques with the dual metal-gate + high-k transistors. The second feature is the extension of 193 nm dry lithography to the 45 nm technology node pitches. Use of these features has enabled industry-leading...
This paper describes the fabrication and performance of uniaxial strained silicon CMOS transistors with NiSi metal gate electrodes and ultra-thin 1.2nm gate oxide. This work offers the first comprehensive evaluation of Si CMOS devices integrating NiSi metal gate (FUSI) process with highly strained Si channels. Performance gains from FUSI gate stack and uniaxial strained Si channels are demonstrated...
An advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented. At 1V and off current of 100nA/mum, transistors have record currents of 1.21mA/mum and 0.71mA/mum for NMOS and PMOS respectively. This industry leading 65nm technology is currently in high volume manufacturing
This paper presents the design, fabrication and characterisation of a high performance 4H-SiC normally-off, trenched and implanted vertical junction field-effect transistor (VJFET). Devices with different trenched mesa widths were designed and their performance investigated. The fabricated VJFETs demonstrated a 3.9Omega resistance at VG=5 V (with negligible gate current) and JD=154 A/cm2, corresponding...
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