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This paper presents circuit techniques that support on-chip SRAM dynamic reliability management to prevent half-selected cell stability failure due to Bias Temperature Instability (BTI) degradation. The proposed techniques monitor the BTI degradation in SRAM cells through a replica row and adjust the WWL voltage level with the assist of a two-phase write operation, where the WWL voltage level is divided...
Lowering power consumption and increasing noise margin have become two central topics in every state of the art SRAM design. Several 8T and 10T cell designs have been reported, improving the cell stability of the conventional 6T. In this paper, we use a fully differential 8T SRAM that removes the half-accessed issue to allow an efficient bit-interleaving implementation. It also consumes less power...
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