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Anomalous threshold voltage increase with area scaling of Mg- or La-incorporated high-k gate dielectrics has great impact on scaled devices. This paper reveals that much amount of Mg or La capping effects for Vt reduction was disappeared with the increase of electron mobility in narrow channel nMISFETs. This phenomenon is explained with absorption of Mg and La into STI from bulk high-k layer. The...
A laminate design technology of metal gates is proposed to improve FET characteristics regardless of EOT and gate dielectric material. The laminated metal gate structures are basically composed of low-Rs(sheet resistance) metal/ WF(work-function)-lowering layer/ WFM(WF determining metal). A thin WFM (~2 nm) laminated by the Si-based WF-lowering layer such as poly-Si or TaSiN brings an additional benefit...
We have investigated the time dependent dielectric breakdown (TDDB) characteristics for a high-k/metal gate pMOSFET under inversion stress. We found that electrons, injected from the cathode, being minority carriers in the gate leakage current play an important role in determining TDDB lifetime and found that the presence of oxygen vacancies in HfSiON determine the electron current mechanism in HfSiON...
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