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A high performance 22/20nm CMOS bulk FinFET achieves the best in-class N/P Ion values of 1200/1100 μA/μm for Ioff=100nA/μm at 1V. Excellent device electrostatic control is demonstrated for gate length (Lgate) down to 20nm. Dual-Epitaxy and multiple stressors are essential to boost the device performance. Dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly...
We demonstrate the smallest FinFET SRAM cell size of 0.063 μm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation...
Standby power is one of the most critical issues in low power chip applications. In this paper, we have investigated the effects of body bias and source bias in 65 nm technology through simulations on SRAM standby current (Isb). The simulation results show a 8X reduction in cell Isb at 125degC FF process corner with a 1.0 V NMOS body bias. This has been experimentally verified on a 16 Mb SRAM testchip...
This paper presents three techniques for improving the effectiveness of the recently proposed adaptive stream detection (ASD) prefetching mechanism. The ASD prefetcher is a standard stream buffer that takes a probabilistic feedback-based probabilistic approach to identifying streams. Its strength lies in its ability to effectively prefetch streams that are as short as two consecutive cache lines,...
To design various electronic papers, the panel designers may adopt different types of electrophoretic materials and active matrix backplanes for resolution, speed, and contrast ratio considerations. The electrical and optical characteristics are different for various application conditions so that a good timing controller should provide an easy way to modify waveforms accordingly. In this paper, we...
A 45 nm high performance technology with 11 level metallization is presented for SOC applications. High performance and density are maintained through new process optimizations that allow the use of less restrictive layouts by eliminating defect generation from strain enhancing processes. Additionally, technology modeling has been made simpler through optimization of key processes to minimize context...
This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power. We make three contributions: (1) we describe a simple power-down policy for exploiting low power modes of modern DRAMs; (2) we show how the idea of adaptive history-based memory schedulers can be naturally extended to manage power and energy; and (3) for situations...
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