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This paper presents a novel diagnosis algorithm for small delay defects (SDD). Faster-than-at-speed test sets are generated by masking long paths in the circuit for testing SDD. The proposed diagnosis technique uses timing upper and lower bound to improve the diagnosis resolution. Also, timing-aware single location at a time (TA-SLAT) technique is proposed to diagnose multiple SDD. Test results of...
This paper presents a design for testability (DfT) technique to reduce the peak power supply noise (PPSN) during scan chain shifting. The proposed partition technique reduces the maximum flip-flop density that belongs to the same test clock. The experimental data on large benchmark circuits show that IR drop are reduced by 38.7% on the average compared with the circuit before optimization. Our proposed...
A systematic flow is described for characterizing, modeling, and simulating single event transient-induced soft errors in cell-based designs. Pulse broadening effects are quantified for a 65 nm CMOS process.
We examine the instability behavior of nanocrystalline silicon (nc-Si) thin-film transistors (TFTs) in the presence of electrical and optical stress. The change in threshold voltage and sub-threshold slope is more significant under combined bias-and-light stress when compared to bias stress alone. The threshold voltage shift after 6 h of bias stress is about 7 times larger in the case with illumination...
This paper presents very-low-voltage (VLV) testing for digital NMOS circuits based on amorphous silicon thin film transistor (a-Si TFT) technology. The proposed VLV testing is an economic alternative to burn-in because the former is non-destructive and can be easily performed on regular ATE in a short time. 140 circuits under test (CUT) of two different design styles are implemented in 8 mm a-Si TFT...
Static power due to leakage current will become a major source of power consumption in the nanometer technology era. In this paper, we propose a simple yet effective technique to reduce both static and dynamic power consumption in the scan test process. The leakage current is restrained by selecting a good primary input vector to control the paths of leakage current during the scan shift process,...
Temperature (T) dependent transport measurements of cylindrical shaped gate-all-around silicon nanowire MOSFETs (SNWFETs) were performed. Single electron tunneling behaviors were observed at 4.2 K and one of the devices exhibited anomalously strong current peak which survived even at room temperature. The observed peak was interpreted as an evidence of transport through single impurities in the channel.
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