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We introduce an innovative dual-depth shallow trench isolation (dual STI) scheme for Ultra Thin Body and BOX (UTBB) FDSOI architecture. Since in the dual STI configuration wells are isolated from one another by the deepest trenches, this architecture enables a full use of the back bias while staying compatible with both standard bulk design and conventional SOI substrates. We demonstrate in 20nm ground...
Planar fully depleted (FD) devices with thin Buried Oxide (BOX) offer the unique ability to incorporate effective back biasing which is a key enabler to build a versatile multi-Vt technology. From a dynamic standpoint, forward back bias lowers Vt and thus boost device performance, whereas reverse back bias increases Vt and thus decreases leakage [1]. From a static point of view the back gate allows...
For the first time, we extensively review to which extent ion implantation is viable for the design of n-FET transistors with gate length down to 20nm in a FDSOI technology. Three implantation schemes are covered and their potential and limitations are presented in terms of technological challenges and electrical performance.
We present a detailed analysis of substrate bias (Vbb) impact on gate induced drain leakage (GIDL) for thin-BOX extremely thin silicon-on-insulator (ETSOI) with BOX thickness (TBOX) ranging from 10 to 50 nm and inversion layer thicknesses (TINV) ranging from 1.1 to 1.3 nm. The GIDL behavior for thin-BOX under various substrate biases (Vbb) and partially depleted SOI (PDSOI) devices with different...
We present UTBB devices with a gate length (LG) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and raised source/drains (RSD). Back bias (Vbb) enables Vt modulation of more than 125mV with a Vbb of 0.9V and BOX thickness of 12nm. This demonstrates the importance and viability of the UTBB structure for multi-Vt and power management applications...
Ca3-xBaxCo4O9 (x = 0~0.4) bulks were prepared by sol-gel and spark plasma sintering (SPS) method, and the effects of preparation process on texture and thermoelectric properties were discussed in detail. The results show that SPS process is helpful to form texture. The bulks are composed of plate-like grains, which are aligned to (001) plane. To some extent, the orientation and density of Ca3Co4O9...
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