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Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization due to conflicts and pollution. Explicit motion of data in these architectures, such as message passing, can provide hints about program behavior that can be used to hide latency and improve cache behavior. However, to make...
There have been several attempts at correcting process variation induced errors by identifying and masking these errors at the circuit and architecture level. These approaches take up valuable die area and power on the chip. As an alternative, we explore the feasibility of an approach that allows these errors to occur freely, and handle them in software, at the algorithmic level. In this paper, we...
A fully reconfigurable radio is a paradigm for wireless communication in which either a network or a wireless node changes its transmission or reception parameters to communicate efficiently avoiding interference with licensed or unlicensed users. Software defined radio is a common hardware platform for multi standard communication that is controlled by software. The goal of the software defined radio...
Nehalem is a family of next-generation IA processors for mobile, desktop and server segments implemented in 45nm high-kappa metal-gate CMOS. The family features a new system architecture, significantly enhanced Core architecture, innovations in power management and modular design. The 4-core 8MB-L3-cache die has 731M transistors. We introduce a coherent point-to- point link called QuickPath Interconnect...
Recently proposed techniques for peak power management involve centralized decision-making and assume quick evaluation of the various power management states. These techniques do not prevent instantaneous power from exceeding the peak power budget, but instead trigger corrective action when the budget has been exceeded. Similarly, they are not suitable for many-core architectures (processors with...
The increasing power dissipation of current processors and processor cores constrains design options, increases packaging and cooling costs, increases power delivery costs, and decreases reliability. Much research has been focused on decreasing average power dissipation, which most directly addresses cooling costs and reliability. However, much less has been done to decrease peak power, which most...
This paper describes the core and I/O clocking architecture of the next generation Intelreg Coretrade micro-architecture processor (Nehalem), designed on a 45 nm process technology. Local PLL placement provides modularity and power-efficient scalability by allowing independent frequency and voltage domains. Fast-locking, low-skew PLLs are used to achieve 56% lock time reduction and 30% long-tem jitter...
This paper describes the next generation Intelreg micro-architecture (Nehalem) 45 nm IA processorpsilas core and I/O clocking architecture. Among the highlights are: configurable clocking, fastlock low-skew PLLs, high reference clock frequencies, analog supply tracking system, adaptive frequency clocking, low jitter Intelreg QuickPath interconnect and Intelreg QuickPath memory controller clock generation,...
An integrated quad-core times86 processor is implemented in a 65nm 11M SOI CMOS process. Based on an enhanced Opterontrade core, the SoC-developed processor employs power- and thermal-management techniques throughout the design. The SRAM cache designs target process variation considerations and future process scalability. A DDR2/DDR3 combo-PHY and HT3 I/Os provide high-bandwidth interfaces.
This paper explores thread scheduling on an increasingly popular architecture: chip multiprocessors with simultaneous multithreading cores. Conventional multiprocessor scheduling, applied to this architecture, will attempt to balance the thread load across cores. This research demonstrates that such an approach eliminates one of the big advantages of this architecture - the ability to use unbalanced...
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