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Cross-point memory framework provides high capacity, low power consumption, and low cost in nonvolatile-memory (NVM) technology [1,2]. Resistive cross-point memory structure is one of the potential candidates with scaling down beyond the flash memory [3]. In order to increase density for cross-point architecture, the vertical diode is integrated for the controller (Fig. 1) without planar MOSFET or...
The electron and hole injection statistics of BE-SONOS NAND Flash is studied for the first time using a 75 nm charge-trapping NAND Flash test chip. By using the incremental step pulse programming (ISPP) method the impact of device variations are minimized and the electron number (N) fluctuation can be identified. We find that both electron and hole injection statistics well follow the Poisson statistics...
Floating gate (FG) devices using barrier-engineered (BE) tunneling dielectric have been studied both theoretically and experimentally. Through WKB modeling the tunneling efficiency of various multi-layer tunneling barriers can be well predicted. Experimental results for FG devices with oxide-nitride-oxide (ONO) U-shaped barrier are examined to validate our model. Furthermore, a large-density array...
A vertical channel SONOS memory, which is compatible with current CMOS process and has four physical storage nodes per unit area, is fabricated and electrically evaluated. Comparing with a planar device, the array cell tuning is much easier since the channel length is no longer limited by array area. After reviewing key performances including program/erase (P/E) speeds, second bit effect, program...
Low current/voltage (1 nA/1.3V) operation of resistive switching memory device using Cu metallic filament in Ge0.2Se0.8 solid-electrolyte has been investigated. This resistive memory device have a large resistance ratio of > 10 at 1 nA current compliance, good endurance of ~105 cycles, and good data retention with a current of 1 nA up to 2×103 seconds. The low resistance state decreases with increasing...
Gate stack etch profile-induced reliability issues are reviewed and discussed. A taper nitride profile, which blocks source/drain (S/D) implantation, induces an unwanted n- region. In other words, residual charges above the junctions can deplete the n- much easily and cut off the channel formation. This will cause poor string resistance distribution, worse endurance behavior, program and erase (P/E)...
Bipolar resistive switching memory device using high-kappa Ta2O5 solid electrolyte in a Cu/Ta2O5/W structure with the device sizes from 0.2-8 mum was investigated. This resistive memory device has a high threshold voltage of 0.75 V, high resistance ratio (RHigh/RLow) of 3times103, good endurance of > 103, and excellent retention at 150degC. The memory device with a low current operation of 5 pA...
Bipolar resistive switching memory device with a low power operation (200 muA/1.3 V) in a W/Ge0.4Se0.6/Cu/Al structure has been investigated. A stronger Cu chain formation can be observed by monitoring both the erase voltage and current. The low resistance state (RLow) decreases with increasing the programming current from InA to 500 muA, which can be useful for multi-level of data storage. This resistive...
Low current/voltage (~10 nA/1.0V) resistive switching memory device in a Cu/Ta2O5/W structure has been proposed. The low resistance state (RLow) of the memory device decreases with increasing the programming current from 10 nA to 1 mA, which can be useful for multi-level of data storage. This resistive memory devices have stable threshold voltage, good resistance ratio (RHigh/RLow) of 5.3times107,...
A novel characterization metric for phase change memory based on the measured cell resistance during RESET programming is introduced. We show that this dasiadynamic resistancepsila (Rd) is inversely related to the programming current (I), as Rd = [A/I] + B. While the slope parameter A depends only on the intrinsic properties of the phase change material, the intercept B also depends on the effective...
A novel phase-change memory cell with a double- confinement structure was proposed and fabricated in this work. By having an additional bottom Ge2Sb2Te5 layer under the electrically confined active region, the heat loss can be effectively prevented. The temperature uniformity over the active region significantly improves and so does the thermal efficiency. Therefore, a low IRESET of about 0.3 mA and...
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