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An layer of Cu6Sn5 intermetallic compound (IMC) is formed during the interfacial reactions between lead-free solder and Cu substrate, and it plays a pivotal role in the reliability of solder joint. There are two different growth morphologies of Cu6Sn5 grains-scalloped grain and prism grain. Scallop grains are commonly formed at the interface during the heating up and isothermal heating. Its growth...
This paper demonstrates the first reliable and low cost airgap BEOL technology, generated at extremely tight dimensions (48 nm pitch) in Cu/ULK. This provides 20% nested-line capacitance reduction relative to the ungapped Cu/ULK baseline. This result is of critical importance, as it validates that airgaps can be extended down to ultrafine wire levels, such as for the 10 nm technology node. Current...
The physical mechanism of the time, emitter lateral dimension (AE) and low-high temperature dependent degradation under mixed-mode stress for C-doped SiGe HBTs (SiGe:C HBTs) on thin-film silicon-on-insulator (SOI) is investigated. We focus on the impact of mixed-mode stress on device characteristics such as base current (IB) and current gain (β) degradation rate, device scaling issue and low-high...
Increasing circuit density in multilevel back-end-of line (BEOL) interconnects is necessary to improve integrated circuit performance and area scaling. Ultra low-k (ULK) dielectrics are used to minimize capacitance for lower power consumption and better capacitance-resistance (RC) performance. However, these materials pose integration and reliability challenges, which have limited our ability to scale...
Reliability tests on packaged ultraviolet light-emitting diodes (LEDs) in the ultraviolet-C (UVC) range (< 280 nm) were performed under various temperatures and currents. At higher case temperature, a greater degradation in output power was observed over 1,000 hours. Degradation in output power was also observed at higher operating currents. Some of the output power degradation can be attributed...
Current extrapolations of accelerated test results to life in long term service may be greatly misleading when it comes to lead free solder joints. Notably, realistic service conditions are almost never well approximated by cycling with a fixed amplitude. However, recent results have demonstrated the consistent breakdown of common damage accumulation rules. In isothermal cycling tests the remaining...
A high performance 22/20nm CMOS bulk FinFET achieves the best in-class N/P Ion values of 1200/1100 μA/μm for Ioff=100nA/μm at 1V. Excellent device electrostatic control is demonstrated for gate length (Lgate) down to 20nm. Dual-Epitaxy and multiple stressors are essential to boost the device performance. Dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly...
Floating gate (FG) devices using barrier-engineered (BE) tunneling dielectric have been studied both theoretically and experimentally. Through WKB modeling the tunneling efficiency of various multi-layer tunneling barriers can be well predicted. Experimental results for FG devices with oxide-nitride-oxide (ONO) U-shaped barrier are examined to validate our model. Furthermore, a large-density array...
Concerning the uncertainty of channels and peak power constraint, we give a new practical layering scheme to do reliable transmission. In our scheme, Walsh matrix is employed to do layer-time coding. Regarding columns of a layer-time coding matrix as layers and rows as time, after Walsh layer-time coding, interference among layers can be removed or diminished by adding rows up. When there are layers...
This paper presents for the first time a full 32 nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack. High speed digital transistors are demonstrated 22% delay reduction for ring oscillator (RO) at same power versus previous SiON technology. Significant matching factor (AVT) improvement (AVT~2.8 mV.um) and low 1/f noise...
The focus of this research was to design a framework to create highly autonomous fault-tolerant distributed sensor networks with plug-and-play capabilities. This would enable diagnosis of faulty sensors and reconfiguration of the network in real time to ensure that the control of the manufacturing process can continue with accurate information in presence of sensor and processing element faults. The...
In this paper the availability and deployment cost analysis of different fiber access networks is presented. We consider both standard and novel architectures for two deployment scenarios, namely in dense and sparse populated areas referred to as collective and dispersive case respectively. In order to demonstrate the cost efficiency of different access network architectures we introduce a cost-reliability...
The effect of annealing conditions on defects and post CMP grain size in electroplated Cu lines is discussed. We have studied the effect of these parameters on interconnect reliability by measuring the electromigration of 'via-fed' structures. A failure criterion of 2% change in initial resistance was used for EM rather than the traditional 20% used for aluminum interconnect. The electromigration...
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