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A 2-GS/s 6-bit flash analog-to-digital converter (ADC) in 90nm CMOS is presented. Using the reference-voltage-interpolated calibration reduces bandwidth requirements on the comparator to enable high sampling rates with low power consumption. The ADC consumes 28 mW and occupies 0.35 mm2. The proposed calibrated technique improves ENOB from 3.0 to 5.1 with an input sinusoid at Nyquist frequency.
A new approach for d irect digital frequency synthesizer (DDFS) with analogue sine conversion is presented. The proposed DDFS adopts the ROM-less architecture with linear DAC to achieve higher speed operation and lower power consumption. Fabricated by 0.18-μm CMOS process, the DDFS employs a 9-bits pipe line accumulator to provide an 8-bits amplitude resolution for the DAC circuit. At 1-GHz clock...
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