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This paper evaluates the degradation process in nMOSFETs with HfO2 gate dielectric and interfacial layer (IL) by 3D Kinetic Monte-Carlo (KMC) method considering multi-trap coupling. The degradation and corresponding trap evolution in a 1-nm EOT dielectric stack with different thicknesses of SiO2 IL is simulated under different gate biases (Vg) and temperature (T). The results indicate that IL can...
This paper presents coupling characteristics of multiple traps in HKMG nMOSFETs by a 3D kinetic Monte-Carlo (KMC) simulator we developed, which includes several fully-coupled multi-physical models: trap generation/recombination, trapping/detrapping to/from channel, metal gate, and the interaction of traps. It shows that activation energy and trapping/detrapping from/to channel/gate impact on coupling...
Design guidelines were proposed to evaluate and optimize the 3D RRAM cross-point architecture by a full-size 3D circuit simulation in SPICE. The performance metrics that were evaluated include the write/read margin, access latency, energy consumption per programming, and the density per bit. Different 3D cross-point architecture including the horizontally stacked or the vertically stacked structure...
3D RRAM array suffers more serious reliability issues than 2D array due to the additional dimension involved. This paper systematically assesses the cell-location-dependent write-access (selected cells) and disturbance issues (unselected cells) for a 3D vertical RRAM array. Using a combination of experiments and simulations, a methodology is developed to enable array-level evaluation by conducting...
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