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A millimeter-wave fully differential power amplifier with broadband performance was implemented in 90-nm CMOS technology. The proposed circuit employed a three-dimensional layout for a cascode power cell to reduce the sensitive parasitic effect. The proposed power amplifier provides a 3-dB bandwidth region ranging from 44.7 to 58.8 GHz, with a maximum small-signal gain of 21.6 dB at 49 GHz. In addition,...
Recently paper-based microfluidic chips have been proposed to achieve microfluidic analysis for many applications. Such chips achieve "lab-on-paper" instead of traditional "lab-on-chips". The paper substrate is attractive because it is cost-effective, easy to use and disposable, fully compatible with most medical/biochemical applications, and offering liquid flow by capillary without...
Pre-bond testing of silicon interposer is difficult due to the large number of nets to be tested and small number of test access ports. Recently, it was proposed to include a test interposer that is contacted with the interposer under test in the testing process. Combining these two interposers provides access to nets that are not normally accessible. Previous synthesis method for test interposer...
Output selection is recently proposed for test response compaction. This scheme achieves zero aliasing, full X-tolerance, and high diagnosability, at the cost of inflated test set and non-trivial hardware overhead. The time/space penalty in test output compaction is mainly attributed to the loss of observability. In previous methods, it was in general assumed that erroneous responses are uniformly...
An Intelligent control unit (ICU) is developed based on a field-programmable gate array FPGA and a digital signal processor DSP for the controlled interruption short circuit currents of high voltage circuit breakers. The sample value messages which meet with IEC61850-9-2LE protocols are received and decoded by the FPGA, at the same time a synchronization method is used to reduce the effects of network...
A test scheme for through-silicon-vias (TSVs) in three-dimensional integrated circuits (3D-ICs) is proposed. The proposed scheme is applicable as long as each die in a 3D-IC is pre-bond testable; as a result, combining this scheme with low-cost DFT features for pre-bond die test leads to a test flow with low overall test cost. A test pattern generation (TPG) method under the proposed test scheme is...
Three-dimensional integrated circuits (3D-ICs) create new test challenges. Because of the limited number of test pads available in pre-bond test, the IR-drop can become a serious problem in delay test. In this paper we present a low-power delay test architecture, in which scan flip-flops are partitioned into groups that can be selected turned off in the capture cycles. As a result, power consumption...
In this paper, we present RAG, an efficient Reliability Analysis tool based on Graphics processing units (GPU). RAG is a fault injection based parallel stochastic simulator implemented on a state-of-the-art GPU. A two-stage simulation framework is proposed to exploit the high computation efficiency of GPUs. Experimental results demonstrate the accuracy and performance of RAG. An average speedup of...
This paper proposed a full-chip testing scheme for 3D ICs to achieve the integrated horizontal/vertical interconnect reliability and yield enhancement with targets of interconnect faults under stuck-at and open fault models. This scheme is based on our previously developed IEEE std. 1500 compatible oscillation-ring (OR) testing methodology and further applies to Through-Silicon-Vias (TSVs)-based 3D...
The electromagnetic coupling between the transmission lines on the same tower brings significant impacts on the secondary arc behavior, which results in requirement for re-optimization of the shunt reactors and the neutral reactor. Equations for calculating the secondary arc current as well as the recovery voltage were developed through establishing distributed parameter-based electromagnetic coupling...
General Purpose computing on Graphical Processing Units (GPGPU) is a paradigm shift in computing that promises a dramatic increase in performance. But GPGPU also brings an unprecedented level of complexity in algorithmic design and software development. In this paper, we present an efficient parallel fault simulator, FSimGP2, that exploits the high degree of parallelism supported by a state-of-the-art...
Based on analyzing the four kinds of faults (over-load, short-circuit, open-phase and electrical leakage) with their characteristics and studying protection principle of mineral motor, the design scheme of intelligent and synthetic protection device using DSP as the chief chip is presented. According to the requirements of system operation, hardware circuits including leakage protection and voltage...
Identifying anomaly detection such as failure and attacks rapidly and accurately over the Internet holds interest of both network operators and researchers. Network behavior analysis (NBA) system is usually disposed over an intranet, passively collects SNMP data or flow data, and uses signature and anomaly mechanisms to identify and analyze interesting network activities, including traffic anomaly...
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