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The increase of standby current of DRAM caused by the HEIP degradation of p-MOSFET and the way to improve the HEIP immunity without the deterioration of performance are reported. The electron trapping at the top region of STI SiN liner is the main cause of the HEIP degradation. To improve the HEIP immunity, several candidates are examined. The large tabbed-gate device and the thicker STI sidewall...
This study proposes an innovative method to measure the variation of cell leakage current. Extreme cell leakage determines DRAM refresh time (tREF). Although the average leakage current from the test element group (TEG) has been the only index for determining cell leakage, it does not provide the distribution of unit cell leakage. We find that cell leakage distribution can be calculated from the slope...
Gate induced drain leakage (GIDL) characteristics were investigated with the recessed channel array transistor (RCAT) for DRAM, using the elevated source drain (ESD). The lower doping concentration of a source-drain region in the ESD structure reduces the electric field, which reduces drain leakage current and also the fluctuation of leakage current. These reductions can enhance the data retention...
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