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The sensitivities of a Monte Carlo simulation tool (PRESTAGE) to variation of input parameters are studied. When calculating the single event upset cross-section induced by proton direct ionization, PRESTAGE calculation results significantly change with changes in the sensitive volume and passivation layer thicknesses. When calculating cross-sections induced by proton indirect ionizations, PRESTAGE...
We demonstrate a 40Gb/s pure photonic packet switch testbed for a datacenter network. It uses a photonic wrap/un-wrap to handle all packet sizes, separate control and data paths, and a synchronization scheme to align packets of all nodes at the photonic switch despite different network fiber lengths.
A new chaotic system is built which is consists of two subsystems. A subsystem is analyzed such as equilibrium, eigenvalue, Lyapunov, dimension and Lyapunov exponent. A practical circuit is designed to realize the system and the experimentation is carried out. The manifold chaotic attractor of the two subsystems is observed in the oscillograph, It is good agree with simulation.
Modular based partially and dynamically reconfigurable (PDR) FPGA system is an ideal solution for run-time image processing system which needs to change the function of the processing unit dynamically. Here we present a new PDR image filter based on our self-developed FDP FPGA Device. In this system, the transition bus (TB) structure is proposed for physical separation of the static/dynamic blocks...
This paper examines the implementation considerations of Compressive Sampling (CS) in Field Programmable Gate Array (FPGA) and proposes computation-free linear projection implementation for CS encoding in imaging applications. A simplified sensing matrix is implemented to eliminate the multiplication and summation processes in the sensing stage. This sensing paradigm does not require all pixels in...
Principles of CIC (cascade integrator comb) filter and DFC (digital-to-frequency converter) which is used in energy calculation are illustrated detailed in this paper. A new structure of 3-order CIC decimation filter is put forward in order meet the requirements of electric power metering chip, and a simple DFC method is presented in order to generate pulses proportional to the active power. VHDL...
In order to solve the problem of precise control of non-linearity system, a digital fuzzy-PID controller is designed by combining the advantages of fuzzy inference and PID controller based on FPGA. First, the model of the controller is established on the platform of Simulink. Simulation result shows that the controller exhibits a good transient response and a stable control action despite of the divergent...
A system module of reactive power measurement is proposed on the basis of analyzing the mathematic model in this paper. A FFT intelligence property (IP) core is designed to estimate the amplitude and phase of harmonic. Two multipliers and a subtraction also are designed to calculate reactive power. Transposing circuit is applied to fix the data in order to reduce error of the system. An adder module...
An efficient implementation of discrete wavelet transform (DWT) in JPEG2000 is designed with low memory and high pipeline architecture. Considering the limited dynamic range of wavelet coefficients, a modified scheme of integer-to-integer discrete wavelet transform based on fixed-point manipulation is proposed by preserving efficiently fractions of coefficients in lifting steps. This scheme ensures...
This paper presents a hybrid image compression scheme based on a block based compression algorithm referred to as Vector Quantization (VQ) combined with the Differential Pulse Code Modulation (DPCM) technique. The proposed image compression technique called the PVQ scheme results in enhanced image quality as compared to the standalone VQ. The generated codebooks for the PVQ scheme are more robust...
This paper presents a hybrid image compression algorithm based on a novel adaptive quantization algorithm referred to as Fast Boundary Adaptation Rule (FBAR) combined with the Differential Pulse Code Modulation (DPCM) technique. The proposed image compression technique results in enhanced image quality as compared to FBAR-based compression. Our proposed system is still much simpler compared to other...
The paper addressed how to design the software radar signal processor based on the software defined radio structure, and discussed the reasons for using the DSP+FPGA and offered an insight into fix on the important parameters of software radio. Attention is concentrated on the construction of algorithm model, simulation the algorithm by Simulink, and some methods for algorithm and architecture mapping...
In order to meet the need of high speed data transfer in ultrasonic inspection nowadays, a PC and USB based high speed digital ultrasonic flaw detector is introduce. The technology of USB (universal serial bus), especially USB2.0 facilitates the connection of PC to peripheral, and accelerates data transfer. By using the USB interface the speed of data transfer is significantly increased, which solved...
In this paper an all digital phase-locked loop (ADPLL) that is based on double edge triggered D-flip-flops (DETDFF) was proposed. By using DETDFF, the functions of bi-directional zero crossing sample and phase detection, which are key issues in the designing process of ADPLL with several new important characteristics, were implemented. In addition, the run speed of each part in the loop was enhanced...
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