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This paper describes the design of an active electrode integrated circuit (IC) for a wearable electrical impedance tomography (EIT) system required for real time monitoring of neonatal lung function. The IC comprises a wideband high power current driver (up to 6 mAp-p output current), a low noise voltage amplifier and two shape sensor buffers. The IC has been designed in a 0.35-μm CMOS technology...
In this paper, an 8-channel area-efficient low-power current-mode analog front-end amplifier (AFEA) is designed for EEG signal recording. The AFEA is composed of eight capacitive coupled transconductors (CCGMs), current-mode band-pass filters (CMBPFs), and programmable current-gain amplifiers (PCGAs) with a multiplexer (MUX), a transimpedance amplifier (TIA), and an offset current cancellation loop...
An 8-channel chopper-stabilized analog front-end amplifier (AFEA) is designed in 65-nm CMOS for continuous EEG signal acquisition. The AFEA is composed of eight capacitively coupled chopper instrumentation amplifiers (CCCIAs) with chopper-stabilized circuits and band-pass filters, a multiplexed transconductor, and a transimpedance amplifier. The CCCIA employs an inverter-based folded-cascode amplifier...
In order to prevent the influence from obstacles on reflector antenna's performance, the installation environment of the reflector antenna is very strict. But on many platforms, the installation position of the reflector antenna cannot be easily changed. Therefore, it is necessary to know the effect of obstacle on the reflector antenna pattern. In this paper we have used simulation method to calculate...
A 2.6 GHz cascode CMOS power amplifier with the derivative superposition (DS) method and the second harmonic control for LTE application is fabricated in TSMC 1P6M 0.18 µm standard CMOS process. The DS method uses two transistors connected in parallel and biased in low and high inversions to compensate for the gm3 and achieves the greater third-order intercept point (IIP3). The second harmonic control...
In this paper, an 8-channel low-power analog front-end amplifier (AFEA) with time-constant-enhanced topology is proposed for neural signal acquisition. The AFEA is composed of eight time-constant-enhanced amplifiers (TCEAs) and high-pass filters (HPFs), a multiplexed transconductor (MGM) and a transimpedance amplifier (TIA). The AFEA is designed and simulated in 65nm CMOS technology. The bandwidth...
In this paper, a new current-mode front-end amplifier for biopotential signal recording system is proposed. A current-mode preamplifier incorporates with an active feedback loop to bypass any dc current generated by tissues is designed as the first stage. A programmable gain stage and a current-mode filter are designed to adjust both gain and the low-pass cutoff frequency, respectively. The current-mode...
In this paper an 8-channel CMOS general-purpose analog front-end (AFE) circuit with tunable gain and bandwidth for biopotential signal recording systems is presented. The proposed AFE consists of eight chopper stabilized pre-amplifiers, an 8-to-1 analog multiplexer, and a programmable gain amplifier. It can be used to sense and amplify different kinds of biopotential signals, such as electrocorticogram...
Two 23 GHz low-noise amplifier (LNA) have been designed and implemented by 45 nm planar bulk-CMOS technology with high-Q above-IC inductors. In the designed LNAs, the structure of cascode amplifier with source inductive degeneration is used. All high-Q above-IC inductors have been implemented by thin-film wafer-level packaging (WLP) technology. The fabricated one-stage LNA has a good linearity where...
In this paper, a low power V-band low-noise amplifier (LNA) using standard 0.13-um CMOS technology is proposed and analyzed. In the proposed LNA, three-stage common-source topology is used instead of cascode configuration to improve the noise performance. The measured LNA gain is 10.9 dB and the simulated noise figure of the proposed LNA is 5.1 dB at 67.8 GHz. Furthermore, the input and output return...
In this paper, a 60-GHz CMOS direct-conversion receiver integrated with a frequency tripler is proposed. The proposed receiver consists of a low-noise amplifier (LNA), a down-conversion mixer, output buffers, and a frequency tripler. This chip is designed using 0.13-um CMOS technology. By using a frequency tripler, the operating frequency of the PLL can be reduced from 60 GHz to 20 GHz. This makes...
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