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This paper presents a multi-PLL clock architecture used in a 4-lane multi-protocol serial link applications. The clock architecture consists of one public LC PLL and four standalone ring PLLs placed within each lane. A swtich capacitor array based LC VCO is used in the LC PLL to enlarge the frequency tuning range and decrease the VCO gain. A two stage pseudodifferential inverter based ring VCO with...
This paper presents a wideband LC PLL designed for multi-protocol serial link applications. Dual LC voltage controlled oscillator (VCO) cores are used to cover a wide frequency range while keeping a high Q factor of the LC tank, and multi-ratio dividers are used to satisfy the multi-protocol requirements. Each LC VCO adopts a 4-bit switch capacitor to increase the frequency tuning range and decrease...
This paper describes the design of a low-jitter source-synchronous link transmitter macro for data rates of 9.6 Gb/s. The transmitter macro consists of 5 data channels plus 1 forwarded-clock channel. A low jitter PLL with bandwidth linearization is employed to achieve 0.66ps rms jitter. The power supply induced jitter is minimized by employing a hybrid clock distribution network which is proposed...
A low power low cost fully integrated single-chip UHF radio frequency identification (RFID) reader for short distance handheld applications is presented in this paper. The IC integrates all building blocks-including an RF transceiver, a PLL frequency synthesizer, a digital baseband and a MCU-in a 0.18 μm CMOS process. A high-linearity RX front-end and a low-phase-noise synthesizer are designed to...
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